1. Field of the Invention
The present invention relates to the field of bus protocols in computer systems and, more specifically, to methods and circuitry for requesting and responding to requests over a bus.
2. Prior Art
Many known computer systems comprise a plurality of modules such as processor modules, memory modules, etc., which communicate over a bus system. Typically, the modules may be under control of a common or synchronized clock signal. Generally such a configuration provides a CPU clock signal on the bus. Individual modules generate signals on the bus synchronous to the CPU clock signal.
A deterministic relationship is assumed to exist during the design of the various modules. Modules, such as the processing unit, may then be designed to add a fixed number of wait states to their access cycles to accommodate slower modules.
Such a system design may require changes to the individual modules if the CPU, clock speed is increased.
Therefore, as one objective of the present invention it is desired to develop a system architecture and bus protocol which allows CPU clock speed to be changed without affecting other modules in the system.
In computer systems, it is further necessary to provide certain configuration information about certain modules to other modules in the system. For example, the processor module may require information regarding the speed of a certain memory module, the type of memory access mode the memory module is capable of supporting (e.g. static column, fast page, burst, etc.), the page size used on dynamic random access memory (DRAM) chips, etc.
Therefore, as a second objective of the present invention it is desired to develop a computer system having a protocol for supporting a variety of module configurations; the protocol allowing for communication of such configuration information between modules in the system.
Known computer systems further typically may utilize a plurality of configuration or "dip" switches. The switches are utilized to provide information to the processor unit regarding the configuration of installed modules. For example, a particular system may be configured with a first memory board having four megabytes of memory and a second memory board having an additional eight megabytes of memory. In this configuration, configuration switches, either on the main system board (motherboard or baseboard) or on the individual add-on modules may be set to indicate four megabytes of memory are installed on the first memory board and eight megabytes of memory are installed on the second memory board.
In such systems, address decode logic may be employed on each memory board in the system. Based on the setting of the configuration switches in the examplary system described above, address decode logic may be employed such that the first board addresses memory in system memory space from memory address 0 to memory address 4M - 1 and the second board addresses memory in the system memory space from memory address 4M to memory address 12M - 1.
It is a third object of the present invention to develop a computer system allowing for communication of information regarding installed memory address space without the requirement of complex user settable configuration switches.
As a fourth object of the present invention it is desired to develop a computer system which does not require separate address decode logic on each memory module in the system.
These and other objects of the present invention will be described in more detail with reference to the detailed description of the present invention and the accompanying drawings.